The present invention relates to a process (method) for controlling the etching profile of a layer of an integrated circuit.
Besides the dimensional control of the etching of the layers of integrated circuits, the control of the etching profiles, that is to say of the spatial law of etching in a direction at right angles to the surface of the substrate of the integrated circuit, is involved in an increasingly sensitive manner in the development of etching techniques in microelectronics.
Following the advent of dry etching, or plasma etching, the control of the profile of the interconnection holes made in the dielectric for isolation between semiconductor or conductor levels was the first problem encountered. In such a case the solution consists in employing anisotropic etching, that is to say comprising only one component at right angles to the surface of the substrate; in particular of the dielectric layer such as SiO2. The control of the slope is obtained by usage or erosion of the photoresist mask.
As shown in FIG. 1a) in relation to a first embodiment of the prior art, this erosion can be isotropic, such an erosion nevertheless exhibiting the disadvantage of an excessively high sensitivity to the effects of charge, that is to say high sensitivity to the surface to be etched, to the distance between patterns and to the size of the patterns. As shown in FIG. 1b, this erosion can also be anisotropic. However, such an erosion makes it necessary for the photoresist mask to be profiled, that is to say to have its profile adapted prior to the actual etching process. The adaptation techniques employed for this purpose in most cases include a heat treatment, such as flow, and turn out to be unsuitable for the production of micron- and, even more so, submicron-sized patterns.
Insofar as the control of the etching profile of the interconnecting materials is concerned, this control has hitherto been essentially limited to that of the anisotropy of etching, that is to say to the control of the vertical character of this profile, that is at right angles to the surface. As shown in FIG. 1c, anisotropic etching of a metal, such as aluminum, requires the passivation of the etching flank, that is to say the formation of a thin layer inhibiting the risk of side attack by the etching agent which, in this particular case, consists of atomic chlorine originating from the C12 molecule. Such a passivation is in most cases obtained by formation and deposition of low-volatility chloro- or fluorocarbon compounds CCl.sub.x or CF.sub.x, originating from the use of the masking photoresist and/or from the cracking of additional gases such as CCl.sub.4, CHCl.sub.3, CF.sub.4, CHF.sub.3, SiCl.sub.4 or NF.sub.3. This mechanism inhibits etching by eliminating any side etching effect on the flanks of the metal. Thus, an anisotropic aluminum etching process which can be employed for the manufacture of integrated circuits, that is to say in which the erosion of the photoresist mask remains compatible with the topography of these circuits, can be used after an appropriate choice of the parameters of the ion etching plasma, such as pressure of the gaseous atmosphere, radio-frequency power, gas flow rate, gas mixture. This choice depends, furthermore, on the design of the reactive ion etching reactor.
Beyond simple anisotropic etching, the control of the slope of the profile of the interconnecting metallic materials offers the technological advantage of making it possible to improve the planarising power and the quality of the deposits of the upper layers such as the intermetallic dielectric or encapsulation layers, whatever the technique of dielectric deposition which is employed, resulting in better behaviour and better reliability of the electronic chips in the medium or long term.
However, the control of the etching profile of a metallic material,such as aluminum, by anisotropic erosion of the masking photoresist, according to FIG. 1b, or by deposition of polymers on the etching flanks while reinforcing the deposit-passivation effect of FIG. 1c, offers a solution which is difficult to implement industrially. In fact, such a result can be obtained only at the cost of an excessively high erosion of the masking photoresist or of a chemical etching environment which is excessively polymerizing and therefore generating particles and, as a result, defects in the definition of the metal level.
The subject of the present invention is the use of a process for controlling the etching profile of a layer, especially a metallic layer, of an integrated circuit, which does not present the abovementioned disadvantages.
Another subject of the present invention is the use of a process for controlling the etching profile of a layer, especially a metallic layer, of an integrated circuit, permitting the use of chemical reactions and products which are not, or are only slightly, polymerizing, and this makes it possible to avoid the appearance of defects in the definition of the level of the layer, especially the metallic layer.
Another subject of the present invention is the use of a process for controlling the etching profile of a layer, especially of a metal layer, of an integrated circuit, permitting an etching process giving rise to a low vertical erosion, i.e. in a direction at right angles to the surface of the substrate of the integrated circuit, of the masking photoresist, this erosion being, according to another objective of the process forming the subject of the invention, made minimal, in order to adapt the process forming the subject of the invention to the conditions of industrial utilisation.
The process for slope etching of the profile of a layer of an integrated circuit, called a layer to be etched, this layer being coated with a layer of masking photoresist, in accordance with the subject of the present invention, is noteworthy in that it consists in performing jointly a passivation of the etching flank of the said layer to be etched and a nonisotropic erosion of the said masking photoresist layer, and this makes it possible to control the slope of the etching flank of the layer to be etched.
The process forming the subject of the invention finds application in the industry for the manufacture of integrated circuits on an industrial scale .